Apple Sr. CAD Engineer – Analog Model Verification Engineer in Beaverton, Oregon
Sr. CAD Engineer – Analog Model Verification Engineer
Typically requires 5+ years of industry experience in digital/mixed-signal modeling.
Analog/RFIC design background, and CAD automation support and development will be helpful.
Proficiency with digital and mixed signal simulators: Incisive/Xcelium, VCS, AMS Designer, CustomSim-VCS, etc.
Strong ability to solve simulation accuracy, speed and capacity issues.
Experience in evaluating simulation and environment related CAD tool/product applications, and driving EDA vendors to meet design requirements.
Proficiency in SystemVerilog (2012), real number modeling, UDT/UDN, wreal, and Verilog-AMS.
Knowledge of the operating principles of common analog, RF and AMS blocks in CMOS technologies. Strong understanding of the implementation of high-level, mixed signal, and behavioral models for such circuits.
Very efficient programming skills and good software development fundamentals in Python, Perl, and SKILL.
Knowledge of the Cadence Virtuoso Design Framework, Virtuoso Schematic Editor, and Analog Design Environment (ADE-L/XL/GXL/Explorer/Assembler), including flow automation and custom netlisting with SKILL.
Ability to provide automations for rapid and dynamic design needs.
Knowledge in Perforce and/or regressions is a plus.
On our team, you will: - Develop, deploy, and support robust, configurable, and scalable tools to enable hardware verification across multiple projects - Identify, capture, and analyze metrics for improved automation reliability and hardware verification performance - Help to debug vendor tool issues - Interact with the DV team to help tackle their problems - Implement new functionality to solve emerging problems or to optimize already existing methods
Education & Experience
MS / PhD preferred in a technical discipline.
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