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Intel Design Automation Engineer in Hillsboro, Oregon

Job Description

In this role as a key member of the Intel Signoff Deployment team, you will have the opportunity to be a part of a world-class team of passionate engineers working in backend signoff flows. You will be responsible for all aspects of static timing, circuit quality checking and/or ECO including developing flows, methodologies and supporting designers on timing analysis, circuit quality checking and signoff ECO closure. In particular, job duties will include:

  • Work closely with design teams to understand and debug Static Timing Analysis, circuit quality and ECO issues

  • Create and maintain flows and scripts to support Static Timing Analysis, circuit quality and ECO

  • Engage with vendors to drive tool quality improvements and fixes

  • Drive Static Timing Analysis, circuit quality and ECO methodology to improve flows for deep submicron designs

  • Own regression and testing of design testcases to improve quality of flows deployed to design team


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related major with 3+ years experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related major with 2+ years experience in the following:

  • Experience in static timing analysis flows and tools

  • VLSI focus and familiarity with Static Timing Analysis, circuit quality and ECO on large high-performance SoC in deep sub-micron technologies

  • In-depth understanding of key timing aspects including cross-talk, OCV effects, margins, and constraints

  • Proficiency in using and debugging industry standard Static Timing Analysis tools such as Primetime

  • Programming in scripting languages Perl and TCL

Preferred Qualifications:

  • Familiarity with circuit modeling, SPICE simulations and timing ECO techniques preferred

  • Understanding of industry standard Synthesis and Place and Route flows would be a plus

  • Strong communication and written skills

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

Other Locations

US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.