Intel Digital Design Engineer in Hillsboro, Oregon

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) as a Digital Design Engineer!

DCG's Datacenter Silicon Development Circuit Design Team is seeking an experienced and hands-on, DDR PHY Micro-Architect to join us in designing Intel's next generation server memory products. In this role you will develop and support digital circuit design for cell libraries as well as perform custom digital circuit design and simulation. Additionally, you will design, develop, modify and evaluate digital electronic parts, components or integrated circuitry for use in digital electronic equipment and other hardware systems. You will also determine design approaches and parameters and perform digital circuit design, verification and layout, data path design and digital block synthesis.

Key Responsibilities include, but are not limited to:

  • Innovate and own DDR PHY level Micro-Architecture and Verilog designs and recommend design trade-offs to optimize power and performance.

  • Ensure the DDR PHY meets the protocol Spec and DFT/DFM requirements. Modify the Verilog Codes for our DDR PHY to support feature and design changes, bug fixes, and validation metrics. Ensure the DDR PHY meets the protocol Spec and Design for Testing (DFT) and Design for Manufacturing (DFM) Requirements.

  • Modify the Verilog Codes to support Structural Design execution, such as ensuring the codes can be synthesized and verified using Static Timing Analysis. Also, verify that the Power UPF passes Spyglass.

  • Reviews Verilog simulation results, both passing and failing tests. Also, ensure the Verilog code passes Lintra and relevant smoke/regression testing.

  • Own and Update the DDR PHY Power UPF, Bumpout, Usage Model, MAS documentation, and Validation Test Plan.

  • Collaborate across functional teams to meet Power, Performance, Schedule, and Area metrics: Core Design, Fullchip, Pre-Silicon and Post-Silicon Validation, Structural Design, Firmware, and BIOS.

  • Mentor and develop technical leadership pipeline.

The ideal candidate will have the following skills in addition to the qualifications listed below.

  • Ability to provide effective, hands on, technical leadership in a results oriented team environment.

  • Excellent verbal and written communication skills.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.

www.intel.com/jobs/datacenter

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:

Bachelor’s degree in Electrical Engineering or equivalent with 6 plus years of industry experience, Master’s degree in Electrical Engineering or equivalent with 4 plus years of industry experience, or a PhD in Electrical Engineering with 2 plus years of industry experience.

  • 5 plus years of experience in Circuit Micro-Architecture definition for DDR4, DDR5, LPDDR4, LPDDR5 designs. DDR4 designs achieved production in high volume and extensive exposure on post-silicon debug and BIOS based PHY training algorithm.

  • 5 plus years of experiences in Verilog Design for DDR3/DDR4/DDR5/LPDDR4/LPDDR5. DDR3/DDR4/LPDDR4 designs achieved production in high volume and exposure on post-silicon debug and BIOS based PHY training algorithm.

Additional Preferred Qualifications:

  • 4 plus years of experience and cross discipline knowledge in any of these areas: Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.

  • 3 plus years of experience and good understanding of LPDDR/DDR JEDEC specifications and related DDR Protocols.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.