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Intel Senior Serial IO Debug Validation Engineer in Hillsboro, Oregon

Job Description

The high-speed serial IO subsystem team within the Xeon Platform Integration and Validation org, located within the Data Platform Group (DPG) is responsible for the validation and verification of our high speed serial IO interfaces for DPG’s next generation platforms. This includes PCIe, CXL (Compute Express Link), etc.

We are looking for an experienced Platform Validation and Debug Engineer, with protocol analysis background/experience, to help us with our Serial IO platform subsystem team validation and debug efforts. In this role, you will be help lead and deliver platform level quality debug/validation efforts, ensuring a positive experience and end to end solution for our customers. You will be responsible for the development of methodologies, execution of validation plans, and debug of issues that arise. You will work across various validation teams both internally and externally as well as engage with Architecture and Design Teams. You will bring your deep understanding of Serial IO design, implementation and debug.

We are looking for someone that will be hands on, get in the lab, use state of the art debug and test equipment to help discover and drive resolution to key issues, as well as working with external customers when needed. If you enjoy the art of debug and you like challenging yourself with leading edge technology, we are interested in hearing from you.

Qualifications

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork, classes and project work, internships, military training, and/or work experience.

Minimum Qualifications

  • 6+ years of post-silicon validation experience and PCI Express Protocol and/or IO validation, debug experience (4+ years if you have a Master’s Degree or 2+ years if you have a PhD)

  • 6+ years of debug tool experience (e.g. protocol analyzers, exercisers and/or Logic analyzers, etc.) (4+ years if you have a Master’s Degree or 2+ years if you have a PhD)

  • Bachelors in Electrical Engineering, Computer Engineering, Computer Science or related degree

Preferred Qualifications:

  • ucode/pcode experience

  • PHY design experience

  • Experience in Microcontroller debug experience on CPU/PCH (pre-si and/or post-si) and/or BMC, SPS/ME

  • Server Platform/Intel Architecture high speed serial IO experience

  • Experience with Python and ITP usage

  • Bug tracking database process and procedures experience

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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