Intel SoC Design Engineer - Scan Validation in Hillsboro, Oregon
Come join Intel's Client Engineering Group, responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.
We are looking for a SoC (System on Chip) Scan Validation Engineer ready to research, design, develop, and test lead Intel designs as we re-imagine how to build SoCs at Intel and in the semiconductor industry. This role is within Intel's highly-regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Austin, Texas, and Penang, Malaysia. Our bold purpose as a company is to "create world-changing technology that enriches the lives of every person on earth" and this role is instrumental in furthering our mission to shape the future of technology.
As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art Scan solutions. In this role you will:
Work as part of a pre-silicon validation team for future Intel SoCs or IPs
Focus on scan validation and scan enabling on silicon.
Work with pre-silicon and post -silicon validation teams to improve scan features, tools and silicon enabling times.
Work closely with post-silicon product engineers on scan pattern validation and silicon enabling.
Pioneer new tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling.
Your responsibilities may include but will not be limited to:
Clock validation to ensure all clocks are enabled and at the correct frequencies for at-speed scan testing
Enabling full chip GLS models and validating scan patterns to ensure content works on first silicon
Scanning isolation validation to ensure scan doesn't break functionally required modes like PLLs, power gates, etc.
Creating detailed scan test plans and tests using written specs, RTL code and other tests as a guide
Validating and enabling scan dump on system boards
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
The ideal candidate will also exhibit a willingness to work across design and validation teams to solve problems.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a Bachelors degree in Computer Science or Computer/Electrical Engineering with 9+ years of work experience - OR - a Masters degree in Computer Science or Computer/Electrical Engineering with 6+ years of work experience.
6+ years of experience with two or more of the following:
Enabling GLS models and debugging issues on scan patterns
Scan/ATPG design, validation or pattern enabling
Reading and interpreting technical specs and Register Transfer Level (RTL) code
Writing validation plans and software to implement those validation plans
2+ years of experience with:
- Programming languages and scripting, such as C, Perl, Python, or Verilog
10+ years of experience with:
Inside this Business Group
The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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