Intel SoC Design Engineer in Hillsboro, Oregon
The Full-Chip Integration team is looking for an SoC Design Engineer to join Design Enablement (DE) team in Technology Development Organization (TD). The charter of the team is to develop physical design methodology for Test Chip lead vehicles which are primarily used for Intel's next generation process development and high-volume certification. The specific role focuses in the layout domain and encompasses engagement with manufacturing on cutting-edge process nodes, facilitation of hierarchical layout convergence and correct-by-construction assembly, IP integration oversight, driving and qualification of design to meet tape-in requirements, and delivery of SOC design to manufacturing.
As a SoC Design Engineer, your responsibilities will include but not be limited to:
Developing layout design methodology and productivity automation for cutting edge process nodes
Working closely with LTD Process Engineers to define critical Design features that needs to be exercised in the early lead vehicle test chips.
Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements
Orchestrating mock full-chip assembly and tape-ins in preparation for the real thing and to provide package and tape-out partners with representative data for planning and product prep
Building and supporting tools, capabilities, methods, and work models for global layout design and convergence
Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Success in this job requires working closely with Engineering, DAs, and manufacturing partners with a goal to robustly tape-in a complex multi-hierarchical SOC within hours of final block completion.
The ideal candidate should exhibit the following behavioral traits:
Verbal and written communication skills
Ability to work well both autonomously and in an intensive, cooperative team environment
Exhibiting strong interest in Layout design
Motivation to continuously learn and drive to push improved layout productivity and efficiency
You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Master's degree in EE or ECE with 1+ years in the following areas:
Hands-on experience with state-of-the-art floorplan, layout design, and verification CAD tools
Experience with layout design rule
Knowledge of Chip floor planning,layoutintegration, layout design rules and schematic/layout comparison debug andvalidation
Software and coding skills (Perl, Python, SKILLand/orTcl)
Comprehension of electrical behavior of materials and insight into ways to improve reliability and manufacturability.
Floorplanningwith ICC2-DPand ability to customize the flow based on design needs.
Exposure toRunsetdevelopment using ICV/Calibreto facilitate automation to improve layout productivity.
Knowledge onSemiconductor device physics
Proven Project Management skills on coordinating and tracking the entire design cycle of a project fromFeature definition to final Tape-in.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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