Intel SOC Global Design/Fabric Conv Specialist in Hillsboro, Oregon
Looking for an SOC Global design engineer well versed in timing convergence and programming to join a senior Xeon-class integration/convergence team. The charter of the sub-team is to drive the specification, development, and convergence of SOC interconnect fabrics and global components necessary to meet the performance, functionality, and DFT/DFM requirements. The team also has a hand in IP coordination and integration, and planning/design/convergence methodology and work model optimization for efficiency and productivity continuous improvement.
In this position, your responsibilities will include but not be limited to:
Specification, design, simulation, and verification of SOC high speed interconnect/network on chip.
Working with IP providers on electrical and layout optimization to balance area and frequency specifications
Working with clocking team to balance skew/power to meet interconnect speed requirements
Working with architecture team to translate performance requirements into latency and frequency specifications for implementation
Participating in the advancement of timing convergence technology and work model
Advancing the state of the art in top-level global fabrics implementation, constantly improving layout and timing convergence KPIs each generation
[optional:] participation in post-Si timing debug and correlation
The ideal candidate should exhibit the following behavioral traits:
Strong verbal and written communication skills
Strong teamwork skills and mentality and the capability of managing a high-intensity, dynamic work environment
Excellent interpersonal skills for interaction with internal and external tool vendors
Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with plus 4+ years of relevant experience or a Master's degree in Electrical/Computer Engineering, Computer Science or related field with 3+ years of relevant experience, or a PhD degree in Electrical/Computer Engineering, Computer Science or related field with 1+ years of demonstrated ability to meet the job requirements.
Your experience must include the following:
Experience with tight technical team interactions for technological advancement and facilitation of stringent timing/clocking convergence goals
Strong familiarity with processor design and convergence
Strong familiarity with static timing analysis concepts
Familiarity of layout and extraction issues associated with leading edge processes
Familiarity with clock distribution theory, approaches, issues
Strong programming and automation development skills (Perl and/or C and/or C++ and Tcl/Tk)
Familiarity with PrimeTime, Fusion Compiler, ICC, Cadence Innovus
Good customer support and collaboration skills spanning multiple design sites
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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