Apple CAD Engineer – Timing for Transistor-Level Flows & Methodologies in Portland, Oregon
CAD Engineer – Timing for Transistor-Level Flows & Methodologies
Typically requires at least 3+ years of hands on experience in timing, STA, CAD/methodology, etc
Proficiency in STA and relevant methodologies for timing closure, signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc
Proficiency in formal/functional/logic-to-circuit equivalence checking (FEC) techniques and implementation a plus
Experience with transistor-level tools such as NanoTime, PathMill, ESP (Verilog to Spice equivalence checking), LEC, HSPICE
Familiar with digital custom circuit designs including dynamic circuit techniques and memories as well as SPICE models and netlists
Experience programming in Perl, TCL, or similar language
Strong communicator who can accurately describe issues and follow them through to completion
In this exciting role, you will: - Collaborate with design teams to understand and debug tool issues and constraints - Build/maintain flows, scripts and methodologies for transistor level analysis - Work closely with both the Design and CAD teams to drive timing, power, signal integrity, and functional verification closure efforts - Perform deep analysis of timing paths to identify key issues - Document and help build guidelines/specs
Education & Experience
BS, MS preferred, degree in technical field.
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